There are numerous teachings within the prior art of address decoding techniques. These decoding techniques have been employed at least since the advent of digital computers. These decoding techniques are not restricted to digital computers, but are currently employed in many electronic applications. Typically, the prior art has employed some type of combinatorial logic using Boolean logic to address and select circuits.
Charge coupled devices (CCDs) have been extensively used in modern imaging applications. These applications include: camcorder markets; high resolution, still imaging applications; and fast frame rate, diagnostic and inspection applications. CCD sensor performance criteria include quantum efficiency, optical fill factor, dark current, lag, smear, and dynamic range. There are numerous factors that make the usage of CCDs not always desirable. Among these are power consumption, and the requirement of a special fabrication process that is not compatible with industry standard CMOS process. CCD imagers require special drive and signal processing electronics that result in increased system (camera) cost.
An alternative approach to using CCDs for image sensing devices is to use a CMOS based image sensor having photo diodes integrated within CMOS based control circuitry. The CMOS process can then be used to integrate the rest of electronics on the same chip. Early versions of such image sensors had individual image sensing elements connected to passive devices and, hence, were called passive pixel sensors. These prior art passive pixel sensors have evolved by employing active devices, such as a readout amplifier, for every pixel to counter the effect of bus capacitance, resulting in a device that is modernly termed active pixel sensors (APS). More recent developments, such as double delta sampling has increased the signal-to-noise performance of APS image sensors. The APS image sensors are presently considered by numerous applications by corporate institutions because of their low cost and their low power consumption.
Any pixel within an APS image sensor array can be randomly addressed by activation of an X address line in combination with at Y address line. For a 512.times.512 pixel sensor, 18 wires are needed to address the pixels, thus requiring 18 more pins on the sensor. Additionally, these address lines have dense decoder demands (a 9 input address decoder is required to individually address the 512 pixels on each of the 512 lines of the sensor). Another disadvantage is the allotment of the routing space required for these address lines.
Moreover, the usage of such a high number of 9 input decoder requires substantial silicon. Typically, a 9-input AND gate is required to implement the decoding with the required random addressing capability. Each of these 9-input AND gate normally comprises 20 or more transistors. Thus, a 512 of these 9-input AND gates may need over 10,240 transistors, and this must be implemented in both the X and the Y directions. In addition, to the substantial spatial requirements, such a decoder also increases the power consumption.
The alternative approach is to use a shift register technique to address various pixels on the sensor. The usage of shift registers for addressing the pixels reduces the overall transistor count substantially. However, conventional shift register techniques do not allow for random addressing of the pixels. The readout of such a conventional shift register based systems is analogous to a camcorder, reading pixel after a pixel in every line, and then one line after another until the end of the frame. That approach does not work well for APS devices because it does not possess the random addressing that is a feature of APS devices.
It should be readily apparent from the foregoing discussion that there remains a need within the art for a device employing address decoding techniques that provide the random addressing techniques required for APS imagers with a reduced gate count.